In general, semiconductor memories for storing data may be classified into two types, i.e., nonvolatile memory and volatile memory. The volatile memory is prone to lose data stored therein when its power supply is interrupted, while the nonvolatile memory may retain information stored therein even when its power supply is off. Compared with other nonvolatile memory technology (such as a magnetic disk drive), the nonvolatile semiconductor memory has the advantages of low cost and high density. Consequently, the nonvolatile memory has been widely applied in many fields including the embedded system such as a personal computer (PC) and its peripherals, a telecom exchange, a cell phone, a network interconnection device, an instrument and an automobile device; and the newly emerged product for storing voice, image and data, such as a digital camera, a digital recorder and a personal digital assistant.
Recently, a nonvolatile memory with a SONOS (silicon-oxide-nitride-oxide-silicon) structure, i.e. SONOS flash memory has been introduced. The nonvolatile memory with a SONOS structure has a very thin cell, so that it is easy to be fabricated and easy to be integrated into, for example, a peripheral region and/or a logic region of integrated circuit.
A method for fabricating a SONOS flash memory has been disclosed in U.S. Pat. No. 6,797,565, which comprises the steps as shown in FIG. 1A: first, a silicon oxide-silicon nitride-silicon oxide (ONO) layer 102 is formed over a silicon substrate 100; then a first polysilicon layer 104 is deposited over the ONO layer 102; a first etch stop layer 106 is formed over the first polysilicon layer 104; a first photoresist layer 107 is spin coated over the first polysilicon layer 106; and a first opening pattern 108 is formed on the first photoresist layer 107 along the direction of bit line through a exposure and development process, the position of the first opening pattern 108 on the first photoresist layer 107 corresponds to the position where the source and drain will be formed.
As shown in FIG. 1B, the first etch stop layer 106 and the first polysilicon layer 104 are dry etched by using the first photoresist layer 107 as a mask, till the ONO layer 102 is exposed. Since a selective etching is not adopted, the etched first etch stop layer 106 and the etched first polysilicon layer 104 have a rectangle section along the direction of word line. The etched first polysilicon layer 104 is used as the gate. Then, the first photoresist layer 107 is removed. An ion implantation is performed to the silicon substrate 100 through the ONO layer 102 by using the gate as a mask, to form the source/drain 101.
As shown in FIG. 1C, a dielectric layer 110 is deposited over the ONO layer 102 and the first etch stop layer 106. The material of the dielectric layer 110 is a low temperature silicon oxide, wherein the low temperature ranges from 200° C. to 500° C. Then, a planarization process is performed to the dielectric layer 110 till the first etch stop layer 106 is exposed. Next, the first etch stop layer 106 is removed to expose the first polysilicon layer 104.
As shown in FIG. 1D, a second polysilicon layer 112 is deposited over the first polysilicon layer 104; a second etch stop layer 114 is deposited over the second polysilicon layer 112; and a second photoresist layer 115 is spin coated over the second etch stop layer 114; and then a second opening pattern 116 is formed on the second photoresist layer 115 along the direction of word line by a exposure and a development process.
As shown in FIG. 1E, the second etch stop layer 114, the second polysilicon layer 112 and the first polysilicon layer 104 are dry etched along the second opening pattern 116 by using the second photoresist layer 115 as a mask, till the ONO layer 112 is exposed; and the second photoresist layer 115 and the second etch stop layer 114 are removed to expose the second polysilicon layer 112, which connects the gates of the SONOS flash memory to form a word line.
FIG. 2 is a top view of a SONOS flash memory fabricated according to the prior art, wherein the reference numeral 110 represents a dielectric layer and 112 represents the second polysilicon layer. FIG. 2A is a sectional diagram of the SONOS flash memory shown in FIG. 2 taken along the line B-B in FIG. 2. The line B-B shows the direction of word line. With reference to FIGS. 1A-1E and FIG. 2A, it may seen that the dielectric layer 110 deposited between the portions of the first polysilicon layer 104 has a rectangle section along the direction of word line, since the first polysilicon layer 104 has a rectangle section along the direction of word line after the first etch stop layer 106 and the first polysilicon layer 104 are etched. The dry etching is an anisotropy etching, that is, the etching functions mainly in the vertical direction and has little effect in the lateral direction. Thus, the portion of the first polysilicon layer 104 at the edge of the dielectric layer 110 may be absorbed by the dielectric layer 110 when the second etch stop layer 114, the second polysilicon layer 112 and the first polysilicon layer 104 are etched to a depth near the ONO layer 102. In this way, the first polysilicon layer 104 on the sidewall of the dielectric layer 110 can hardly be etched away by the weak lateral etching, while the vertical etching has little effect on the sidewall of the dielectric layer 110 either. Accordingly a polysilicon residue 120 will be formed on the sidewall of the dielectric layer 110, which may cause a short circuit between the memory cells.
In the method of fabricating SONOS flash memory according to the prior art, since the dielectric layer between the portions of the first polysilicon layer has a rectangle section along the direction of word line, and the dry etching is an anisotropy etching, that is, the etching functions mainly in the vertical direction and has little effect in the lateral direction, the portion of the first polysilicon layer at the edge of the dielectric layer may be absorbed by the dielectric layer when the second etch stop layer, the second polysilicon layer and the first polysilicon layer are etched to a depth near the ONO layer. In this way, the first polysilicon layer on the sidewall of the dielectric layer can hardly be etched away by the weak lateral etching, while the vertical etching has little effect on the sidewall of the dielectric layer either. Accordingly, the polysilicon residue will be formed on the sidewall of the dielectric layer, which may cause a short circuit between the memory cells.